VLSI based hardware accelerator for compute intensive routing applications

Abstract

Identifying the most optimal paths (or routes) in a network is one of the most extensively studied problems in the field of graph theory. The advent of complex applications such as the VLSI place and route, vehicle navigation, high-speed communication, graph matching, dynamic robot path planning, etc. justify the need to devise a high-speed route computation unit. It is well recognised that a significant improvement in performance could be realised if the route computations can be efficiently ported to hardware. Since the classical algorithms do not lend well for hardware porting, there exists a need to devise new techniques that are capable of providing parallelism at the hardware level.