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dc.contributor.authorLu, Shanguo.en_US
dc.date.accessioned2008-09-17T09:01:48Z-
dc.date.available2008-09-17T09:01:48Z-
dc.date.copyright2001en_US
dc.date.issued2001-
dc.identifier.urihttp://hdl.handle.net/10356/2385-
dc.description.abstractThis thesis is aimed to implement turbo decoder with various iteratie decoding algorithms, and to compare their hardware requirements, speeds achievable and error performances.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computing methodologies::Pattern recognition-
dc.titleFPGA implementation of turbo decoders with various decoding algorithmsen_US
dc.typeThesisen_US
dc.contributor.supervisorGunawan, Erryen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.description.degreeMaster of Philosophyen_US
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