dc.contributor.authorXiao, Shuen_US
dc.date.accessioned2008-09-17T09:03:58Z
dc.date.accessioned2017-07-23T08:28:22Z
dc.date.available2008-09-17T09:03:58Z
dc.date.available2017-07-23T08:28:22Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationXiao, S. (2006). Power-balanced instruction scheduling for pipelined VLIW architectures. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/2483
dc.description.abstractThe focus of this thesis is on techniques for minimizing power variation for the duration of the whole program.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
dc.titlePower-balanced instruction scheduling for pipelined VLIW architecturesen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorLai Ming-Kit, Edmunden_US
dc.description.degreeDOCTOR OF PHILOSOPHY (SCE)en_US


Files in this item

FilesSizeFormatView
SCE-THESES_233.pdf1.318Mbapplication/pdfView/Open

This item appears in the following Collection(s)

Show simple item record