Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/2500
Title: | FPGA implementation of MELP decoder | Authors: | Tey, Peng Chiou. | Keywords: | DRNTU::Engineering::Computer science and engineering::Computing methodologies::Pattern recognition | Issue Date: | 2002 | Abstract: | The MELP (Mixed Excitation Linear Prediction) Vocoder uses a mixture of noise and pulses in the synthesizer to simulate the residual signal obtained after LPC spectral whitening of input speech. This mixture removes the characteristic buzziness from the traditional LPC synthesized speech. In addition, a third voicing state is introduced that removes thumps and tonal noises. | URI: | http://hdl.handle.net/10356/2500 | Schools: | School of Computer Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | SCSE Theses |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
SCE-THESES_249.pdf Restricted Access | 3.43 MB | Adobe PDF | View/Open |
Page view(s) 10
864
Updated on Mar 16, 2025
Download(s)
5
Updated on Mar 16, 2025
Google ScholarTM
Check
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.