High performance hardware security components

Abstract

A considerable amount of recent research has focused on hardware implementations of cryptographic algorithms and protocols because of the higher performance and the better security they provide, compared to software-based implementations. Software-based implementations are more appealing in that they can support a range of different security protocols, whereas hardware implementations are generally developed for a specific protocol. To improve the flexibility of hardware implementations, it would be desirable to be able to support multiple security protocols on the same platform. Thus it would be useful to design a security coprocessor module which is able to unify the arithmetic computations for supporting protocols like Rivest, Shamir, and Adleman (RSA) and Elliptic Curve Cryptosystem (ECC) over Galois fields GF(p) and GF(2p). Additionally, while specialized hardware security components are perceived to provide better security, their widespread use has presented new and different opportunities for cryptanalysis attacks. Rather than trying to break the cryptographic algorithm, attackers are focusing on attacking deficiencies in the hardware implementation. These attacks, called side channel attacks, are a powerful technique for determining sensitive data based on timing measurements, power analysis, fault analysis, etc. Hence, the ability to defend against cryptanalysis of the hardware must also be considered.