Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/2622
Title: High performance multiply-accumulate unit for residue number system DSP core
Authors: Pretthy, A. P.
Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures
Issue Date: 2000
Abstract: High speed computing continues to inspire the researchers, especially in the more demanding areas like digital signal processing and multimedia applications. In this regard multiplier designs and multiplier-accumulator units (MAC) have long been a topic of interest to the digital community due to their extensive use in almost every digital design. Many innovative techniques have been used in the past for the design of multipliers by making use of the number theoretical properties of finite fields. Even though a few of these designs were based on the structure of polynomial rings, the properties of finite integer rings have not been exploited to their full potential so far.
URI: http://hdl.handle.net/10356/2622
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Theses

Files in This Item:
File Description SizeFormat 
PretthyAP00.pdf
  Restricted Access
Main report15.81 MBAdobe PDFView/Open

Page view(s) 50

376
Updated on Nov 23, 2020

Download(s) 50

5
Updated on Nov 23, 2020

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.