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https://hdl.handle.net/10356/2665
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jimson Mathew | en_US |
dc.date.accessioned | 2008-09-17T09:07:23Z | |
dc.date.available | 2008-09-17T09:07:23Z | |
dc.date.copyright | 2000 | en_US |
dc.date.issued | 2000 | |
dc.identifier.uri | http://hdl.handle.net/10356/2665 | |
dc.description.abstract | The use of Residue Number Systems (RNS) in highly computation intensive applications have been found to provide fast solutions. But its advantages are often eclipsed by the large area and hardware complexity of the conversion circuitry. With the recent development in conversion circuitry and also due to the advantages offered by VLSI technology, RNS is being used increasingly in many signal processing applications. In this context, we propose a few reverse converter architectures that save on hardware and are faster compared to the conventional ones. | en_US |
dc.rights | Nanyang Technological University | en_US |
dc.subject | DRNTU::Engineering::Computer science and engineering::Computing methodologies::Pattern recognition | |
dc.title | Framework for optimal residue-to-binary converters in VLSI | en_US |
dc.type | Thesis | en_US |
dc.contributor.supervisor | Radhakrisnan, Damu | en_US |
dc.contributor.school | School of Computer Engineering | en_US |
dc.description.degree | Master of Applied Science | en_US |
item.grantfulltext | restricted | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | SCSE Theses |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
JimsonMathew00.pdf Restricted Access | Main report | 14.1 MB | Adobe PDF | View/Open |
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