Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/2717
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dc.contributor.authorLiu, Po Ching.en_US
dc.contributor.authorSiek, Liter.en_US
dc.date.accessioned2008-09-17T09:13:45Z-
dc.date.available2008-09-17T09:13:45Z-
dc.date.copyright2000en_US
dc.date.issued2000-
dc.identifier.urihttp://hdl.handle.net/10356/2717-
dc.description.abstractThis project was initiated for the effective design and layout of input protection devices. Scope of this work includes setting up prototype ESD testing environment, studying the layout of commercial chips and the ESD threshold voltages, then test our own design on the chip fabricated.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials-
dc.titleOptional layout of input / output protection devicesen_US
dc.typeResearch Reporten_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.reportnumberRP 40/90-
item.fulltextWith Fulltext-
item.grantfulltextrestricted-
Appears in Collections:EEE Research Reports (Staff & Graduate Students)
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