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Title: Chemical and mechanical polishing for realization of advanced planarization schemes and patterned SOI structures
Authors: Goh, Wang Ling.
Tse, Man Siu.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Issue Date: 2001
Abstract: First part aimed at producing varied planarization schemes that are suitable for both the Shallow Trench Isolated test structures and the Static Random Access Memory structures. Second part, the direct-wafer bonding process was employed to arrive at the Silicon-On-Insulator substrates.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Research Reports (Staff & Graduate Students)

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