Turbo codec for software radio receivers

Abstract

Turbo codes are a class of state-of-the-art error correction codes, which has been demonstrated to approach the Shannon?s channel capacity with manageable decoding complexity. In spite of its remarkable error correction power, the signal processing involved in Turbo decoding, especially for Turbo codes with large code memory, is still considered to be too complex, hence too slow or too costly to realise, for many applications in practice. The main goal of this project is to design and develop modularized and re-usable software and hardware cores (programs) for Turbo encoders and decoders (codecs). Such cores will be useful for integration into a software radio test-bed for rapid prototyping and flexible investigations of a wide range of real-time communication applications. To this end, DSP (digital signal processor) and VHDL (Very High-speed Hardware Description Language) program codes for implementing Turbo coding and decoding in high-performance DSP and FPGA (field programmable gate array) platforms will be developed, optimized, verified, and benchmarked. In addition, a new class of iterative decoding algorithms based on SPC (single parity check) component decoding will also be studied for its suitability as very low- complexity SISO (soft-in-soft-out) component decoders for a wide range of channel codes.