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|Title:||Development and IC implementation of signal processing algorithms for a digital noise reduction hearing aid||Authors:||Chang, Joseph.
Tong, Yit Chow.
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2004||Abstract:||The overall objectives of this research project pertain to the prevalent and serious problem of poor speech intelligibility experienced by hearing instrument (hearing aid) users in everyday noisy environments due to the poor signal-to-noise ratio (SNR, typically 13 dB SNR) of speech in such environments. voltage (1.1 - 1.4V) micropower (10s-100s Ws) mixed-signal (analogue signal conditioners and digital circuits) integrated circuits for the realisation of an intelligent speech processing hearing instrument that features noise reduction and for considerations of practicality, one that does not dissipate excessive power. Specifically, we report our work on: In this report, we describe our work in the design of low 1. Analogue Class D Amplifiers 2. Digital Class D Amplifiers 3. Noise Reduction Algorithm 4. Digital Filterbank 5. Asynchronous Logic Digital Signal Processor||URI:||http://hdl.handle.net/10356/2905||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Research Reports (Staff & Graduate Students)|
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