Development of IEEE 802.11a wireless LAN test-bed

Abstract

An IEEE 802.1la WLAN test-bed is being developed. The test-bed aims to provide a FPGA (field programmable gate array) development platform that allows individual PHY functional blocks to be investigated. This report presents the FPGA implementation of the IEEE 802.1la physical layer. The WLAN transceiver system is first designed using the ADS software where design parameters are carefully determined to meet the standard requirements before proceeding to FPGA implementation. The implementation covers the OFDM base-band modulator-demodulator, scrambler, interleaving, convolutional encoder and Viterbi decoder. With a theoretical internal clock rates as high as 400MHz, the selected FPGA chips provide a suitable programmable hardware platform for achieving the high data rate requirements of 54Mbps in this WLAN test-bed.