Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/2910
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dc.contributor.authorLaw, Choi Looken_US
dc.contributor.authorGuan, Yong Liangen_US
dc.contributor.authorBasuki Endah Priyantoen_US
dc.contributor.authorLi, Kwet Pin Chi Vanen_US
dc.date.accessioned2008-09-17T09:17:00Z
dc.date.available2008-09-17T09:17:00Z
dc.date.copyright2004en_US
dc.date.issued2004
dc.identifier.urihttp://hdl.handle.net/10356/2910
dc.description.abstractAn IEEE 802.1la WLAN test-bed is being developed. The test-bed aims to provide a FPGA (field programmable gate array) development platform that allows individual PHY functional blocks to be investigated. This report presents the FPGA implementation of the IEEE 802.1la physical layer. The WLAN transceiver system is first designed using the ADS software where design parameters are carefully determined to meet the standard requirements before proceeding to FPGA implementation. The implementation covers the OFDM base-band modulator-demodulator, scrambler, interleaving, convolutional encoder and Viterbi decoder. With a theoretical internal clock rates as high as 400MHz, the selected FPGA chips provide a suitable programmable hardware platform for achieving the high data rate requirements of 54Mbps in this WLAN test-bed.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems
dc.titleDevelopment of IEEE 802.11a wireless LAN test-beden_US
dc.typeResearch Reporten_US
dc.contributor.supervisorLaw, Choi Looken_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
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Appears in Collections:EEE Research Reports (Staff & Graduate Students)
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