Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3025
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dc.contributor.authorLiu, Po Ching.en_US
dc.contributor.authorChin, Edward Hsi Ling.en_US
dc.date.accessioned2008-09-17T09:19:05Z-
dc.date.available2008-09-17T09:19:05Z-
dc.date.copyright1986en_US
dc.date.issued1986-
dc.identifier.urihttp://hdl.handle.net/10356/3025-
dc.description.abstractProject studies the critical portions of the layout of some VLSI circuits to enhance our up-to-date techniques of circuit design. Memory chips are selected as the targets of study because they have finer and denser layout patterns than most custom chips.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits-
dc.titleStudy on the layout of some commercial VLSI circuitsen_US
dc.typeResearch Reporten_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.reportnumberRP 15/86-
item.grantfulltextrestricted-
item.fulltextWith Fulltext-
Appears in Collections:EEE Research Reports (Staff & Graduate Students)
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