Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3114
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dc.contributor.authorParthasarathy Srinivasa Raghavan.en_US
dc.date.accessioned2008-09-17T09:22:34Z-
dc.date.available2008-09-17T09:22:34Z-
dc.date.copyright2002en_US
dc.date.issued2002-
dc.identifier.urihttp://hdl.handle.net/10356/3114-
dc.description.abstractThis dissertation elaborated on the most popular low power CMOS circuit and power reduction techniques. A special punch is given on the Adiabatic Quasi-Static CMOS logic of power reduction, followed by the proposal of “Reduced swing Aqs-CMOS/ASL logic.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleLow power CMOS circuit design using adiabatic logicen_US
dc.typeThesisen_US
dc.contributor.supervisorLau, Kim Teenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Consumer Electronics)en_US
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