Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3197
Title: VHDL synthesis of Montgomery modular multiplier
Authors: Sarasvathi Thangaraju.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2005
Abstract: This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed in this work where Montgomery algorithm was implemented using an iterative design reduces the area usage in detriment of response time while the second architecture where Montgomery Modular Multiplication (MMM) was implemented using the systolic array reduces time response in detriment of area requirement. The speedup in modular computations using systolic array is due to the instantiation of components resulting in parallel computation.
URI: http://hdl.handle.net/10356/3197
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
EEE-THESES_1083.pdf
  Restricted Access
27.87 MBAdobe PDFView/Open

Page view(s) 5

915
Updated on Apr 22, 2021

Download(s)

6
Updated on Apr 22, 2021

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.