Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3269
Title: Design of a 54x54-bit multiplier using radix-16 redundant binary booth encoding
Authors: Soh, Sing Yu.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2006
Abstract: In this project, some of these multiplying coefficients were chosen as fundamental multiplying coefficients, and any other multiplying coefficient could be represented as an RB number which consists of two of these fundamental multiplying coefficients or their inverses. The RB partial product generator (RBPPG) was used to generate RB partial products. These RB partial products were added in the RB adder (RBA) array block. Some of the RBA cells in the RBA circuit were optimised for the multiplier in this project.
URI: http://hdl.handle.net/10356/3269
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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