Please use this identifier to cite or link to this item:
Title: High speed, low jitter CMOS analog PLL for clock recovery application
Authors: Sudhaleswar Behera.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2003
Abstract: This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriate topologies, dead zone elimination in PFD and reduction of charge sharing and clock feed through in Charge Pump. This thesis discusses all the issues briefly and applies same methodologies to the above design. Moreover, since this PLL uses differential structure, and hence works at reduced voltage swing, it is not only has the potential of operating at high frequency but also dissipate less power.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
7.98 MBAdobe PDFView/Open

Page view(s) 20

Updated on Mar 6, 2021


Updated on Mar 6, 2021

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.