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|Title:||Resolving p-type transistor drain saturation current (IDsat) off-target issue for 0.3um logic device||Authors:||Tan, Ai Kiam||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2002||Abstract:||Transistor optimization is required for good device performance especially on those devices with off-center electrical se (ET) specifications. In this thesis, the author explores various possible options to bring a particular 0.3?m device Logic Dual gate oxide PMOS transistor IDsat to electrical test target so as to ensure optimum device performance and yield.||URI:||http://hdl.handle.net/10356/3325||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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