Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3339
Title: Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
Authors: Tan, Albert Chong Kit
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2003
Abstract: Aggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical failure analysis (EFA) and physical failure analysis (PFA) techniques were applied to tackle this problem. The root cause was successfully identified as incomplete contact hole etch for (a) the contact hole between the digitline (bitline) and the memory cell transistor and (b) the contact hole between the memory cell transistor and the memory cell capacitor, resulting in either open circuit or high resistance.
URI: http://hdl.handle.net/10356/3339
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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