Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM

Abstract

Aggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical failure analysis (EFA) and physical failure analysis (PFA) techniques were applied to tackle this problem. The root cause was successfully identified as incomplete contact hole etch for (a) the contact hole between the digitline (bitline) and the memory cell transistor and (b) the contact hole between the memory cell transistor and the memory cell capacitor, resulting in either open circuit or high resistance.