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dc.contributor.authorTan, Albert Chong Kiten_US
dc.date.accessioned2008-09-17T09:27:47Z
dc.date.available2008-09-17T09:27:47Z
dc.date.copyright2003en_US
dc.date.issued2003
dc.identifier.urihttp://hdl.handle.net/10356/3339
dc.description.abstractAggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical failure analysis (EFA) and physical failure analysis (PFA) techniques were applied to tackle this problem. The root cause was successfully identified as incomplete contact hole etch for (a) the contact hole between the digitline (bitline) and the memory cell transistor and (b) the contact hole between the memory cell transistor and the memory cell capacitor, resulting in either open circuit or high resistance.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Microelectronics
dc.titleResolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAMen_US
dc.typeThesisen_US
dc.contributor.supervisorLau, Wai Shingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Microelectronics)en_US
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