Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3390
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dc.contributor.authorTan, Teck Heng.en_US
dc.date.accessioned2008-09-17T09:29:09Z-
dc.date.available2008-09-17T09:29:09Z-
dc.date.copyright2004en_US
dc.date.issued2004-
dc.identifier.urihttp://hdl.handle.net/10356/3390-
dc.description.abstractRecommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the current Chartered Semiconductor 0.18 urn and 0.25 urn CMOS technologies.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuits-
dc.titleDesign of high performance CMOS latches and flip-flopsen_US
dc.typeThesisen_US
dc.contributor.supervisorYeo, Kiat Sengen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Consumer Electronics)en_US
item.grantfulltextrestricted-
item.fulltextWith Fulltext-
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