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https://hdl.handle.net/10356/3390| Title: | Design of high performance CMOS latches and flip-flops | Authors: | Tan, Teck Heng. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits | Issue Date: | 2004 | Abstract: | Recommend ways to implement the various Double Edge Triggered Flip-Flop (DETFF) so that it can operate at the highest possible clock frequency, low enough operating nominal voltage and less power consumed by exploring various design circuit topologies and coming out with the best one with the current Chartered Semiconductor 0.18 urn and 0.25 urn CMOS technologies. | URI: | http://hdl.handle.net/10356/3390 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Theses |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| EEE-THESES_1257.pdf Restricted Access | 19.89 MB | Adobe PDF | View/Open |
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