dc.contributor.authorSharma Uditen_US
dc.date.accessioned2008-09-17T09:31:32Z
dc.date.accessioned2017-07-23T08:31:15Z
dc.date.available2008-09-17T09:31:32Z
dc.date.available2017-07-23T08:31:15Z
dc.date.copyright2007en_US
dc.date.issued2007
dc.identifier.citationSharma, U. (2007). Integrated platform for design and verification of digital FIR filters. Master’s thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/3520
dc.description.abstractThis work aimed at creating a unified platform to automate the generation of VHDL codes for the physical synthesis of FIR filters in both direct and transposed direct form filters. The aim was to provide designers and researchers with a tool to analyze the physical performances of different filter solutions in terms of VLSI area, delay and power consumption. Many benchmark filters were collected for such evaluation. This platform also performs a functional verification of the VHDL codes by running parallel simulations in a simulator and comparing the final output with its own response to randomly generated stimuli, thereby avoiding manual supervision.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
dc.titleIntegrated platform for design and verification of digital FIR filtersen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorJong Ching Chuen (EEE)en_US
dc.description.degreeMASTER OF ENGINEERING (EEE)en_US


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