Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3559
Title: Realization of trenched SOI structure using wafer bonding technique
Authors: Teo, Kim Poh.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Issue Date: 2001
Abstract: In this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.
URI: http://hdl.handle.net/10356/3559
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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