Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3559
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dc.contributor.authorTeo, Kim Poh.en_US
dc.date.accessioned2008-09-17T09:32:22Z-
dc.date.available2008-09-17T09:32:22Z-
dc.date.copyright2001en_US
dc.date.issued2001-
dc.identifier.urihttp://hdl.handle.net/10356/3559-
dc.description.abstractIn this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic packaging-
dc.titleRealization of trenched SOI structure using wafer bonding techniqueen_US
dc.typeThesisen_US
dc.contributor.supervisorGoh, Wang Lingen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeDoctor of Philosophy (EEE)en_US
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