Timing analysis of interconnect networks

Abstract

Timing analysis of high-order networks has been an important issue in system study. The delay is one of the important parameters to characterize a system and can be obtained from the transfer function of the system. With smaller feature sizes and increasing clock frequencies of today's semiconductor technology, interconnections between logic gates may actually be the dominant contributors of delay. In addition, interconnect effects such as ringing, reflection, crosstalk, dispersion and attenuation may corrupt logic signals and degrade system performance. These effects are not always handled appropriately, accurately or efficiently by the present levels of circuit simulators.