dc.contributor.authorCao, Yien_US
dc.date.accessioned2010-04-23T01:30:43Z
dc.date.accessioned2017-07-23T08:28:53Z
dc.date.available2010-04-23T01:30:43Z
dc.date.available2017-07-23T08:28:53Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationCao, Y. (2006). Timing analysis of interconnect networks. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/35722
dc.description195 p.en_US
dc.description.abstractTiming analysis of high-order networks has been an important issue in system study. The delay is one of the important parameters to characterize a system and can be obtained from the transfer function of the system. With smaller feature sizes and increasing clock frequencies of today's semiconductor technology, interconnections between logic gates may actually be the dominant contributors of delay. In addition, interconnect effects such as ringing, reflection, crosstalk, dispersion and attenuation may corrupt logic signals and degrade system performance. These effects are not always handled appropriately, accurately or efficiently by the present levels of circuit simulators.en_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
dc.titleTiming analysis of interconnect networksen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.contributor.supervisorTan Eng Chongen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (SCE)en_US


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