Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3585
Full metadata record
DC FieldValueLanguage
dc.contributor.authorThe, Yen Ju.en_US
dc.date.accessioned2008-09-17T09:32:58Z-
dc.date.available2008-09-17T09:32:58Z-
dc.date.copyright2005en_US
dc.date.issued2005-
dc.identifier.urihttp://hdl.handle.net/10356/3585-
dc.description.abstractAn integrated circuit design for low supply voltage applications and high quality performance becomes a challenging task in recent years. This report presents a low voltage, low power, low noise and high power supply rejection ratio (PSRR) operational amplifier to drive a resistive load of 10k Ohm in parallel with a capacitive loadof70pF.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits-
dc.titleDesign of a low noise CMOS Op-Amp with high PSRRen_US
dc.typeThesisen_US
dc.contributor.supervisorSiek, Literen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Integrated Circuit Design)en_US
item.grantfulltextrestricted-
item.fulltextWith Fulltext-
Appears in Collections:EEE Theses
Files in This Item:
File Description SizeFormat 
EEE-THESES_1432.pdf
  Restricted Access
11.66 MBAdobe PDFView/Open

Page view(s) 20

550
Updated on Nov 26, 2021

Download(s) 50

23
Updated on Nov 26, 2021

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.