Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3585
Title: Design of a low noise CMOS Op-Amp with high PSRR
Authors: The, Yen Ju.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2005
Abstract: An integrated circuit design for low supply voltage applications and high quality performance becomes a challenging task in recent years. This report presents a low voltage, low power, low noise and high power supply rejection ratio (PSRR) operational amplifier to drive a resistive load of 10k Ohm in parallel with a capacitive loadof70pF.
URI: http://hdl.handle.net/10356/3585
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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