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|Title:||Development of NTU CMOS process for SiGe BiCMOS technology||Authors:||Wang, Jianpeng.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2002||Abstract:||Wafer fabrication was completed in the Micro Fabrication laboratory (MFL) on two types of starting substrate. Electrical measurement of the fabricated devices showed that selected parameters in the DOE slightly missed the target values. Based on the electrical measurement results, a new set of parameters for DOE is proposed for another round of wafer fabrication.||URI:||http://hdl.handle.net/10356/3663||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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