Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3757
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dc.contributor.authorWong, David Wing Fatt.en_US
dc.date.accessioned2008-09-17T09:36:55Z-
dc.date.available2008-09-17T09:36:55Z-
dc.date.copyright2001en_US
dc.date.issued2001-
dc.identifier.urihttp://hdl.handle.net/10356/3757-
dc.description.abstractIn this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits-
dc.titleLayout design for input/output transistorsen_US
dc.typeThesisen_US
dc.contributor.supervisorYeo, Kiat Sengen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Consumer Electronics)en_US
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