dc.contributor.authorYang, Lieyongen_US
dc.date.accessioned2008-09-17T09:38:44Z
dc.date.accessioned2017-07-23T08:31:26Z
dc.date.available2008-09-17T09:38:44Z
dc.date.available2017-07-23T08:31:26Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationYang, L. (2006). Copper-ultra low k porous SiLK integration for deep submicron integrated circuits. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/3838
dc.description.abstractThe integration of Cu and ULK porous SiLK using different barriers on blanket and patterned wafers has been investigated. This includes characterizations of ULK porous SiLK, Ta based barrier on ULK structures and Ta(N)/SiCN/ULK SiLK structures, and integration of Cu-ULK porous SiLK with different barriers on blanket and patterned wafers. The thermal stability, interaction and electrical properties of different structures were comparatively investigated by using various techniques. The single damascene lines were fabricated of Cu and ULK porous SiLK with different barrier layers in 0.13 µm technology. The line resistance, line to line leakage and breakdown voltage were evaluated at various conditions. Furthermore, effects of plasma treatment and additional SiCN layer on the electrical performance and thermal stability of the Cu/barrier/ULK structures were evaluated. Finally, the thickness of SiCN was also optimized by comparing the electrical performance of the samples with different SiCN thickness.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
dc.titleCopper-ultra low k porous SiLK integration for deep submicron integrated circuitsen_US
dc.typeThesisen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorP. D. Foo
dc.contributor.supervisorZhang Dao Huaen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US
dc.identifier.doihttps://doi.org/10.32657/10356/3838


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