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https://hdl.handle.net/10356/3842
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yang, Tong Jiang | en_US |
dc.date.accessioned | 2008-09-17T09:38:49Z | |
dc.date.available | 2008-09-17T09:38:49Z | |
dc.date.copyright | 2003 | en_US |
dc.date.issued | 2003 | |
dc.identifier.uri | http://hdl.handle.net/10356/3842 | |
dc.description.abstract | The designed Frequency Divider consists of two major parts, Dual-Modulus Prescalar (DMP) and PS-Sharing Counter. Design of the DMP is presented with consideration of low power consumption, while the emphasis of Frequency Divider is placed on the design of new PS-Sharing Counter. The PS-sharing Counter is proposed based on pulse-swallow concept to replace conventional Programmable Counter and Swallow Counter. It has advantage of less hardware, by nature, less hardware occupies less die area and consumes less power supply than conventional design does. | en_US |
dc.rights | Nanyang Technological University | en_US |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | |
dc.title | Frequency divider for general-purposed phase-locked loop frequency synthesizer | en_US |
dc.type | Thesis | en_US |
dc.contributor.supervisor | Ma, Guo Jian | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Master of Science (Integrated Circuit Design) | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | restricted | - |
Appears in Collections: | EEE Theses |
Files in This Item:
File | Description | Size | Format | |
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EEE-THESES_1664.pdf Restricted Access | 10.85 MB | Adobe PDF | View/Open |
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