CMOS building blocks for 10+Gb/s clock data recovery circuit
Date of Issue2007
School of Electrical and Electronic Engineering
The design of a clock data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design of a half-rate high speed CDR is described, following a top-down design procedure. VHDL-AMS, which is the acronym of the VHDL (VHSIC Hardware Description Language) for Analog and Mixed-Signal, is used to implement the behavioral model of the whole system in the early and mid-stage of the design process.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits