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|Title:||CMOS building blocks for 10+Gb/s clock data recovery circuit||Authors:||Liu, Haiqi||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2007||Source:||Liu, H. (2007). CMOS building blocks for 10Gb/s clock data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The design of a clock data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design of a half-rate high speed CDR is described, following a top-down design procedure. VHDL-AMS, which is the acronym of the VHDL (VHSIC Hardware Description Language) for Analog and Mixed-Signal, is used to implement the behavioral model of the whole system in the early and mid-stage of the design process.||Description:||157 p.||URI:||https://hdl.handle.net/10356/39032||DOI:||10.32657/10356/39032||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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