Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/39032
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dc.contributor.authorLiu, Haiqien
dc.date.accessioned2010-05-21T04:37:46Zen
dc.date.available2010-05-21T04:37:46Zen
dc.date.copyright2007en
dc.date.issued2007en
dc.identifier.citationLiu, H. (2007). CMOS building blocks for 10Gb/s clock data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/39032en
dc.description157 p.en
dc.description.abstractThe design of a clock data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design of a half-rate high speed CDR is described, following a top-down design procedure. VHDL-AMS, which is the acronym of the VHDL (VHSIC Hardware Description Language) for Analog and Mixed-Signal, is used to implement the behavioral model of the whole system in the early and mid-stage of the design process.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen
dc.titleCMOS building blocks for 10+Gb/s clock data recovery circuiten
dc.typeThesisen
dc.contributor.supervisorGoh Wang Lingen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en
dc.identifier.doi10.32657/10356/39032en
item.grantfulltextopen-
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Appears in Collections:EEE Theses
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