High-speed CMOS pipelined subranging ADC
Date of Issue2006
School of Electrical and Electronic Engineering
This dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated for high-speed low-power application. The proposed architecture includes one coarse ADC plus two interleaved fine ADCs incorporating with pipeline and doubling sampling techniques. Contrasting to conventional subranging architectures, the system maximizes the throughput via elimination of extra idle time and eliminates a sample-andhold (S/H) circuit. Besides, a new sliding feedback capacitor technique, using time constant reduction concept, is proposed to enhance the speed of coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatches so as to reduce nonlinearity arising from interleaving action. Other well-established circuit techniques like bottom-plate sampling, distributed sampling, autozeroing, and interpolation are employed for complete ADC design.
DRNTU::Engineering::Electrical and electronic engineering