Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/39087
Title: High-speed CMOS pipelined subranging ADC
Authors: Fan, Xianping
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2006
Source: Fan, X. (2006). High-speed CMOS pipelined subranging ADC. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: This dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated for high-speed low-power application. The proposed architecture includes one coarse ADC plus two interleaved fine ADCs incorporating with pipeline and doubling sampling techniques. Contrasting to conventional subranging architectures, the system maximizes the throughput via elimination of extra idle time and eliminates a sample-andhold (S/H) circuit. Besides, a new sliding feedback capacitor technique, using time constant reduction concept, is proposed to enhance the speed of coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatches so as to reduce nonlinearity arising from interleaving action. Other well-established circuit techniques like bottom-plate sampling, distributed sampling, autozeroing, and interpolation are employed for complete ADC design.
Description: 206 p.
URI: https://hdl.handle.net/10356/39087
DOI: 10.32657/10356/39087
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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