Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/39087
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dc.contributor.authorFan, Xianpingen_US
dc.date.accessioned2010-05-21T04:40:37Z
dc.date.available2010-05-21T04:40:37Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationFan, X. (2006). High-speed CMOS pipelined subranging ADC. Doctoral thesis, Nanyang Technological University, Singapore.
dc.identifier.urihttp://hdl.handle.net/10356/39087
dc.description206 p.en_US
dc.description.abstractThis dissertation presents a new 10-bit subranging analog-to-digital converter (ADC) dedicated for high-speed low-power application. The proposed architecture includes one coarse ADC plus two interleaved fine ADCs incorporating with pipeline and doubling sampling techniques. Contrasting to conventional subranging architectures, the system maximizes the throughput via elimination of extra idle time and eliminates a sample-andhold (S/H) circuit. Besides, a new sliding feedback capacitor technique, using time constant reduction concept, is proposed to enhance the speed of coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatches so as to reduce nonlinearity arising from interleaving action. Other well-established circuit techniques like bottom-plate sampling, distributed sampling, autozeroing, and interpolation are employed for complete ADC design.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen_US
dc.titleHigh-speed CMOS pipelined subranging ADCen_US
dc.typeThesisen_US
dc.contributor.supervisorChan Pak Kwongen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeDoctor of Philosophy (EEE)en_US
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Appears in Collections:EEE Theses
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