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|Title:||Cordic BPSK demodulator||Authors:||Alappat Vintu Jose||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2006||Abstract:||The objective of the project is to design a ground station demodulator for a Low Earth Orbit satellite that is intended to be launched in 2008. The BPSK modulated data from the satellite is expected to arrive with a frequency of 16KHz (+/- 400Hz), where the intended data rate is 4KHz. This data comprises of the telemetric signals to be transferred from the satellite to the ground station. Coherent demodulation is required so carrier synchronization is done at the demodulator using second order loop comprising of first order loop filer. Designing over digital hardware is preferred following the various advantages of digital implementation. Emergence of high speed FPGAs made it possible to choose it for the implementation. In addition, this demodulator is to be combined with various other modules related to the higher layers of present application. Therefore, the present design is targeted to run on Field Programmable Gate Arrays (FPGA). Coherent BPSK demodulation requires a pair of multipliers which will be mapped onto floating point multipliers in FPGAs which consume a lot of hardware. It also requires Sine and Cosine calculations which make the design inefficient. Look up tables can be used to store the values of Sine and Cosine values of all the possible angles. This might reduce computational complexity but consumes a lot of space. So a new computational algorithm called CORDIC is implemented which avoids the use of multipliers and trigonometric function generators making the design efficient. This requires a very less entries to be stored in the ROM.||Description:||116 p.||URI:||http://hdl.handle.net/10356/39107||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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