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Title: Three-dimensional (3D) finite element modeling of stress distribution and migration in Cu interconnects
Authors: Anson Heryanto
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2007
Abstract: Consistent improvements in integrated circuit density and performance have been amply demonstrated over the past 20 years by using transistor scaling, a model for simultaneously improving transistor density, performance, functionality and cost per function. In the transistor scaling sub-micron technology, the fact showed that interconnect delay starts to dominate the gate delay. Copper was introduced as a primary interconnect material in integrated circuit in 1997 by IBM due to its lower resistivity than aluminum.
Description: 56 p.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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