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https://hdl.handle.net/10356/39142
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Anson Heryanto | en_US |
dc.date.accessioned | 2010-05-21T04:45:37Z | |
dc.date.available | 2010-05-21T04:45:37Z | |
dc.date.copyright | 2007 | en_US |
dc.date.issued | 2007 | |
dc.identifier.uri | http://hdl.handle.net/10356/39142 | |
dc.description | 56 p. | en_US |
dc.description.abstract | Consistent improvements in integrated circuit density and performance have been amply demonstrated over the past 20 years by using transistor scaling, a model for simultaneously improving transistor density, performance, functionality and cost per function. In the transistor scaling sub-micron technology, the fact showed that interconnect delay starts to dominate the gate delay. Copper was introduced as a primary interconnect material in integrated circuit in 1997 by IBM due to its lower resistivity than aluminum. | en_US |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering | en_US |
dc.title | Three-dimensional (3D) finite element modeling of stress distribution and migration in Cu interconnects | en_US |
dc.type | Thesis | en_US |
dc.contributor.supervisor | Pey Kin Leong | en_US |
dc.contributor.school | School of Electrical and Electronic Engineering | en_US |
dc.description.degree | Master of Science (Microelectronics) | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | restricted | - |
Appears in Collections: | EEE Theses |
Files in This Item:
File | Description | Size | Format | |
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EEE_THESES_NEW_61.pdf Restricted Access | 7.19 MB | Adobe PDF | View/Open |
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