Nanoscale strained-Si/SiGe and double-gate MOSFET modeling.
Date of Issue2007
School of Electrical and Electronic Engineering
A new approach to modeling non-classical CMOS devices, such as strainedsilicon (s-Si) and double-gate (DG) MOSFETs, is presented. We have employed a unified regional, non-pinned surface-potential based modeling approach, which is consistent with the prior development for bulk-MOS formulations. The key idea is to develop unified models with the correct physics and boundary conditions built into them, so that there is a seamless transition of models among different device structures like bulk, DG, SOI, and strained silicon. Threshold-voltage models are derived for surfaceand buried-channel strained-silicon MOSFETs based on the 1-D Poisson equation.
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits