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Title: Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range
Authors: Yu, Xiaopeng
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2006
Source: Yu, X. (2006). Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The wireless communication industry is currently experiencing a tremendous growth. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver. Currently, there exist several different standards of operation; thus a multi-standard frequency synthesizer is desirable for operations under different wireless systems. The objective of this project is to design the most critical building blocks for the multi-GHz frequency synthesizers. All proposed circuits are realized on cost effective CMOS technology. Two prescalers, implemented with the dynamic CMOS circuit and the imbalanced phase switching technique are proposed to achieve lower power consumption for a higher operating frequency. The GHz operation of all-stage programmable counter is first achieved in this work by proposing a new re-loadable bitcell. To achieve the multi-band operation, a VCO with a wide tuning range of 5-6 GHz and a good phase noise performance is designed. By combining with other low frequency building blocks, a complete 5-6 GHz frequency synthesizer is realized to cover both the IEEE 802.11a and the HIPERLAN II standards.
DOI: 10.32657/10356/3940
Rights: Nanyang Technological University
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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