dc.contributor.authorYu, Xiaopengen_US
dc.identifier.citationYu, X. (2006). Fully-integrated CMOS building blocks for phase-locked loops in the multi-GHz range. Doctoral thesis, Nanyang Technological University, Singapore.
dc.description.abstractThe wireless communication industry is currently experiencing a tremendous growth. The frequency synthesizer, which is usually formed by a Phase-Locked Loop (PLL), is a major and critical component of a wireless transceiver. Currently, there exist several different standards of operation; thus a multi-standard frequency synthesizer is desirable for operations under different wireless systems. The objective of this project is to design the most critical building blocks for the multi-GHz frequency synthesizers. All proposed circuits are realized on cost effective CMOS technology. Two prescalers, implemented with the dynamic CMOS circuit and the imbalanced phase switching technique are proposed to achieve lower power consumption for a higher operating frequency. The GHz operation of all-stage programmable counter is first achieved in this work by proposing a new re-loadable bitcell. To achieve the multi-band operation, a VCO with a wide tuning range of 5-6 GHz and a good phase noise performance is designed. By combining with other low frequency building blocks, a complete 5-6 GHz frequency synthesizer is realized to cover both the IEEE 802.11a and the HIPERLAN II standards.en_US
dc.rightsNanyang Technological Universityen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
dc.titleFully-integrated CMOS building blocks for phase-locked loops in the multi-GHz rangeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.contributor.supervisorLin Yiqun
dc.contributor.supervisorDo Manh Anhen_US
dc.description.degreeDOCTOR OF PHILOSOPHY (EEE)en_US

Files in this item


This item appears in the following Collection(s)

Show simple item record