Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/3990
Title: Low power low voltage adder cells for digital multiplier
Authors: Zhang, Mingyan
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2004
Abstract: As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal processors and microprocessors, are subjects of perpetual research interest in VLSI design. This thesis deals with the design of low power high performance arithmetic circuits through design innovation and optimization in a bottom-up approach begins at the transistor level.
URI: http://hdl.handle.net/10356/3990
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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