Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/40183
Title: Design of a high speed CMOS analog comparator
Authors: Chen, Qi.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2010
Abstract: The comparators are widely used in the process of converting analog signals to discrete signals; as such they are required to perform at high speed. To avoid noise from triggering the comparator wrongly, hysteresis is included. However, in CMOS, offset voltage between input differential pair is quite significant, hence proper design is required to achieve high performance both in speed and accuracy which is allowing the widest input and output dynamic range at a supply voltage of 1.2V. This report is to introduce the fundamentals on the characterizations and applications of comparator. Different approaches in the design of the comparator have been studied by verifying the theoretical design with extensive simulations. Hence the combination of open-loop and regenerative comparator is proposed for high speed operations in circuit level design and simulation results are also listed in the report. Finally, the IC layout has been designed and simulated.
URI: http://hdl.handle.net/10356/40183
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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