Please use this identifier to cite or link to this item:
Title: Improvement in speed performance through transistor process optimization
Authors: Zheng, You.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2003
Abstract: This thesis presents the means to achieve higher speed yield for CMOS logic circuits through transistor optimization. Experiments were carried out to study the effect of each process condition on transistor drive current and its timing parameter. Based on the obtained results, selection of process conditions to achieve desired transistor drive current are presented. A linear model has been developed to predict the transistor drive current based on in-line measurement data.
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
5.51 MBAdobe PDFView/Open

Page view(s)

Updated on Sep 23, 2023


Updated on Sep 23, 2023

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.