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https://hdl.handle.net/10356/4049| Title: | Power optimization in data path allocation for high-level synthesis | Authors: | Zheng, Yuhong. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Power electronics | Issue Date: | 2001 | Abstract: | This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits. | URI: | http://hdl.handle.net/10356/4049 | Schools: | School of Electrical and Electronic Engineering | Rights: | Nanyang Technological University | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Theses |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| EEE-THESES_1850.pdf Restricted Access | 2.57 MB | Adobe PDF | View/Open |
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