Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/4049
Title: Power optimization in data path allocation for high-level synthesis
Authors: Zheng, Yuhong.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Issue Date: 2001
Abstract: This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.
URI: http://hdl.handle.net/10356/4049
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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