Please use this identifier to cite or link to this item:
Title: Power optimization in data path allocation for high-level synthesis
Authors: Zheng, Yuhong.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Issue Date: 2001
Abstract: This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
  Restricted Access
2.57 MBAdobe PDFView/Open

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.