Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/40686
Title: Design of the low-voltage CMOS sample-and-hold amplifier
Authors: Li, Xiao Liang.
Keywords: DRNTU::Engineering
Issue Date: 2010
Abstract: A sample and hold circuit is used as a front-end sampler for the analog-to-digital converters. High-speed and low-power applications are more and more preferred. A fully differential CMOS sample and hold amplifier (SHA) is designed in this project. It is based on flip-around architecture. Double sampling technique is used to achieve high speed without much extra power consumption. Bottom plate sampling and bootstrapping technique are also implemented to reduce clock feedthrough and improve linearity of the circuit. The operational transconductance amplifier (OTA) designed here uses folded cascode structure with both PMOS and NMOS input to increase input swing. Regulated cascode is used to increase the gain of the OTA. The SHA is implemented based on 0.18 μm CMOS technology. Using 1.8 V power supply and a signal swing of 0.6 Vpp, the SHA has achieved a resolution of 9 bits at a sampling rate of 400 MSample/s, with power consumption of 4.54 mW.
URI: http://hdl.handle.net/10356/40686
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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