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|Title:||Gold nano particles for nanowire growth formed by thin film thermal annealing process||Authors:||Aung, Nyein Chan||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Semiconductors||Issue Date:||2010||Abstract:||Nanotechnology has received a lot of interest lately that will directly or indirectly benefit our daily lives. With the use of nanotechnology, researchers and scientists are now able to fabricate materials at a molecular scale. A great deal of effort has been made to fabricate one-dimensional nanostructured materials for their unique dimension and physical properties. In microelectronics, researchers are attracted to the potentials that silicon nanowires and nanowire arrays can provide . The use of nanotechnology enables scientists and researchers to build more powerful and lightweight devices. Nanowires can be synthesized from self-assembled nanoparticles, droplets or clusters of thin film metal film. Therefore, research for metal nano templates for developing semiconductor nanowires is intensely conducted to be able to do mass production of semiconductor nanowires for future integration researches and technology revolution in microelectronic industries. In this project, creating gold nano templates formed by thin film thermal annealing process is researched. The size and uniformity of gold nanoparticles are critical as the size of nanoparticles will determine the size of nanowires grown. The transport, optical and thermoelectric properties of nanowires varies as the size of these varies. Density of gold nanoparticles is also important as it is more cost effective to have highly dense nanowires. Some parameters of gold nano templates forming process can be varied to control the size of gold nanoparticles and they are thermal annealing method, crystal orientation, gold deposition layer thickness, annealing temperature and annealing time. In this project two different thermal annealing processes is used-Furnace and Rapid Thermal Process (RTP). Different crystal orientation – 100 and 111; different thickness – 1nm, 3nm, 5nm, 10nm and 15nm and different annealing temperature – 400°C, 600°C, 800°C and 1000°C are used in the experiments.||URI:||http://hdl.handle.net/10356/40713||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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